Asih Setiarini
Pusat Penelitian Elektronika dan Telekomunikasi
Profil Sivitas
Pendidikan
S2 di NCYU, Chia Yi, Taiwan
M.Sc. in Electrical Engineering, September 2012-Juli 2014,GPA : 3.91
Spesifikasi bidang pada analog integrated circuits dan neuromorphic vision chip
Judul Thesis: A CMOS Biologically Expansion/Contraction Motion Sensor and Its Implementation on Z-Motion Direction/Velocity Detection
Jurnal : CT Chiang, A Setiarini, "A cmos biologically expansion/contraction motion sensor and its implementation on z-motion direction/velocity detection," IEEE Sensors Journal,vol. 15, no.4, pp. 2166 - 2176, April 2015
S1 di UB, Malang
S.T Teknik Elektro, September 2006-Februari 2010, GPA : 3.84
Judul Skripsi: Analyzing and Designing 2 to 4 Decoder Emitter Couple Logic (ECL)
Jurnal : A Darmawansyah, A Setyarini, "ANALYZING AND DESIGNING 2 TO 4 DECODER EMITER COUPLE LOGIC (ECL)," IJECS-IJENS, vol. 11, no.6, pp. 21-26, 2012
SMA Negeri 3 Malang, Agustus 2003-Juli 2006
SMP Negeri 5 Malang, Agustus 2000-Juli 2003
SD Negeri Tulus rejo V, 1994 - 2000
Pengalaman
Instrument and Control Engineer of PT. Adhi Karya (Persero) Tbk, EPC Division, project: PLTU Tarahan Lampung 2x100 MW, 2010- 2011. Research assistant of VLSI lab, NCYU, 2012 – 2014. Project: CMOS image sensor. Job function : Analog integrated circuits, biomedical electronics, image sensor circuits and system. Job description : Design the schematic circuit, layout, measurement. Lecturer in State Polytechnic of Madiun (2015-2018).
Kegiatan